1. Field of the Invention
The invention relates to a non-volatile memory, and particularly relates to a controller device and an operation method for a non-volatile memory with a 3-dimensional architecture.
2. Description of Related Art
The techniques of NAND flash memory have been developed to exhibit a 3-dimensional architecture. FIG. 1 is a schematic perspective view illustrating a flash memory 100 with a 3-dimensional architecture. As shown in FIG. 1, a bit line 110, an upper selector 120, a wordline 130, and a lower selector 140 are stacked on a substrate 150. In the flash memory 100 with the 3-dimensional architecture, a plurality of the wordlines 130 are stacked between the upper selector 120 and the lower selector 140. In addition, the number of layers of the wordlines 130 is determined based on design requirements. A plurality of channels 160 penetrate through the upper selector 120, the wordlines 130, and the lower selector 140, as shown in FIG. 1.
FIG. 2 is a schematic top view illustrating the flash memory 100 with the 3-dimensional architecture shown in FIG. 1. FIG. 3 is an equivalent circuit diagram of the channel 160 shown in FIGS. 1 and 2. The flash memory 100 with the 3-dimensional architecture shown in FIG. 3 has five layers of the wordlines 130, which are respectively labeled as wordlines 130_1, 130_2, 130_3, 130_4, and 130_5. The channel 160 shown in FIG. 3 has an upper switch 161 and a lower switch 163. A first terminal of the upper switch 161 is coupled to a corresponding bit line 110. A control terminal of the upper switch 161 is controlled by a control signal DSG of the upper selector 120. A first terminal of the lower switch 163 is coupled to a source line 170 of the substrate 150. A control terminal of the lower switch 163 is controlled by a control signal SSG of the lower selector 140. The channel 160 shown in FIG. 3 further includes five floating gate transistors 162_1, 162_2, 162_3, 162_4, and 162_5, and gates of the floating gate transistors 162_1, 162_2, 162_3, 162_4, and 162_5 are respectively controlled by the wordlines 130_1, 130_2, 130_3, 130_4, 130_5. The floating gate transistors 162_1, 162_2, 162_3, 162_4, and 162_5 are serially connected between a second terminal of the upper switch 161 and a second terminal of the lower switch 163, as shown in FIG. 3.
The flash memory with the 3-dimensional architecture solves some issues of the conventional flash memory with a 2-dimensional architecture, but also results in some other issues. Some common issues include data retention characteristics, read disturbance, or program disturbance, which may result in variation of voltage distributions of memory cells and consequently reduce the reliability. The flash memory with the 2-dimensional architecture and the flash memory with the 3-dimensional architecture have different characteristics. These different characteristics have different influences on the durability of NAND flash memory. A main difference is that the NAND flash memory with the 3-dimensional architecture has greater wordline-to-wordline variation. Distributions of error bits among different layers of wordlines are not uniform.
FIG. 4 is a schematic view illustrating a distribution of data voltage of the flash memory 100 with the 3-dimensional architecture shown in FIGS. 1 to 3. Here, it is assumed that the floating gate transistors 162_1, 162_2, 162_3, 162_4, and 162_5 are in multi-level cell (MLC) structures. A horizontal axis of FIG. 4 represents voltage, and a vertical axis of FIG. 4 represents quantity of distribution. A read voltage (also referred to as threshold voltage) of the MLC flash memory includes an upper page read voltage VtU1, an upper page read voltage VtU2, and a lower page read voltage VtL. Taking the wordline 130_1 (details of the rest wordlines 130_2, 130_3, 130_4, 130_5 may be inferred by referring to the descriptions of the wordline 130_1) as an example, FIG. 4 illustrates four normal distribution curves 401, 402, 403, and 404. The normal distribution curve 401 shows that a memory cell (floating gate transistor) connected with the wordline 130_1 has a data voltage distribution of a memory cell whose upper page data is “1” and lower page data is “1”. The normal distribution curve 402 shows that the memory cell (floating gate transistor) connected with the wordline 130_1 has a data voltage distribution of a memory cell whose upper page data is “0” and lower page data is “1”. The normal distribution curve 403 shows that the memory cell (floating gate transistor) connected with the wordline 130_1 has a data voltage distribution of a memory cell whose upper page data is “0” and lower page data is “0”. The normal distribution curve 404 shows that the memory cell (floating gate transistor) connected with the wordline 130_1 has a data voltage distribution of a memory cell whose upper page data is “1” and lower page data is “0”.
Referring to FIG. 4, when a data voltage of a memory cell is lower than the read voltage VtL, the lower page data of the memory cell may be determined as “1”. When the data voltage of the memory cell is greater than the read voltage VtL, the lower page data of the memory cell may be determined as “0”. When the data voltage of the memory cell is lower than the read voltages VtU1 and VtU2, or the data voltage of the memory cell is greater than the read voltages VtU1 and VtU2, the upper page data of the memory cell may be determined as “1”. When the data voltage of the memory cell is between the read voltage VtU1 and VtU2, the upper page data of the memory cell may be determined as “0”. Accordingly, based on the read voltages VtU1, VtU2, and VtL, the data voltage of the memory cell may be converted into corresponding data.
Due to factors such as data retention characteristics, read disturbance, or program disturbance, the voltage distribution of the memory cell may change and thus reduce the reliability. The variations of voltage distributions of wordlines at different layers may differ. If the data voltage output by the memory cell becomes lower or higher, the normal distribution curve may be shifted. For example, as shown in FIG. 4, an extent to which the normal distribution curve of the wordline 130_2 shifts rightward is greater than an extent to which the normal distribution curve of the wordline 130_1 shifts rightward, and an extent to which the normal distribution curve of the wordline 130_3 shifts rightward is greater than an extent to which the normal distribution curve of the wordline 130_2 shifts rightward. Shifting of the data voltage may result in more error bits in corresponding data that are read or converted.
The conventional NAND flash memory controller adopts error checking and correcting (ECC) solutions such as a Bose-Chaudhuri-Hocquengh (BCH) code algorithm or a low density parity check (LDPC) code algorithm. The conventional controller adopts a fixed parity bit length to correct data having error bits. The conventional ECC solutions work well in the flash memory with the 2-dimensional architecture, as the flash memory with the 2-dimensional architecture has uniform voltage distributions. However, the conventional ECC solutions do not work effectively in the NAND flash memory with the 3-dimensional architecture, because the error bits among different wordlines are not distributed uniformly. If the same ECC solution (with the same parity bit length) is used for each wordline in the NAND flash memory with the 3-dimensional architecture, a parity bit length of a wordline with a smaller shift of data voltage is over-configured, and the performance of the storage device may thus be affected.